The invention relates to a method for controlling a converter having at least two phase modules, which each have an upper and a lower valve branch, which each have at least two series-connected two-pole subsystems, with a constant, freely variable number of subsystems of each phase module being operated such that their terminal voltages are in each case equal to a capacitor voltage across the energy storage capacitor in the associated subsystem, with the remaining subsystems of this phase module being operated such that their terminal voltages are equal to zero.
A polyphase converter is known from DE 101 03 031 A1. FIG. 1 illustrates a circuit arrangement of a converter such as this, in more detail. According to this circuit arrangement, this known converter circuit has three phase modules, which are each annotated 100. These phase modules 100 are each electrically conductively connected on the DC voltage side by a respective connection P or N to a positive and a negative DC voltage busbar P0 and N0. There is a DC voltage Ud between these two DC voltage busbars P0 and N0. Each phase module 100 has an upper and a lower valve branch T1, T3 and T5, as well as T4 and T6, respectively. Each of these valve branches T1 to T6 has a number of two-pole subsystems 11 which are electrically connected in series. Four of these subsystems 11 are shown for each valve branch T1, . . . , T6 in this equivalent circuit. Two-pole subsystems 12 (FIG. 3) can also be electrically connected in series instead of the two-pole subsystems 11 (FIG. 2). Each junction point between two valve branches T1 and T2, T3 and T4 or T5 and T6 of a phase module 100 forms a respective connection L1, L2 or L3 of this phase module 100 on the AC voltage side. Since, in this description, the converter has three phase modules 100, a three-phase load, for example a three-phase motor, can also be connected to their connections L1, L2 and L3, which are also referred to as load connections, on the AC voltage side.
FIG. 2 shows one embodiment of a two-pole known subsystem 11 in more detail. The circuit arrangement shown in FIG. 3 represents a functionally completely equivalent variant, which is likewise known from DE 101 03 031 A1. These known two-pole subsystems 11 and 12 each have two semiconductor switches 1, 3 and 5, 7 which can be switched off, two diodes 2, 4 and 6, 8, and a unipolar energy storage capacitor 9 and 10. The two semiconductor switches 1 and 3, as well as 5 and 7, respectively, which can be switched off are electrically connected in series, with these series circuits being connected electrically in parallel with a respective energy storage capacitor 9 or 10. One of the two diodes 2, 4 and 6, 8 is electrically connected in parallel with each semiconductor switch 1 and 3, or 5 and 7, respectively, which can be switched off such that these diodes 2, 4 and 6, 8 are electrically connected back to back in parallel with the corresponding semiconductor switches 1, 3, 5 or 7 which can be switched off. The unipolar energy storage capacitor 9 or 10 in the respective subsystem 11 or 12 comprises either a capacitor or a capacitor bank composed of a plurality of such capacitors with a resultant capacity C0. The connecting point of the emitter of the respective semiconductor switch 1 or 5 which can be switched off and the anode of the respective diode 2 or 6 forms a connecting terminal X1 of the respective subsystem 11 or 12. The connecting point of the two semiconductor switches 1 and 3 which can be switched off and of the two diodes 2 and 4 form a second connecting terminal X2 of the subsystem 11. The connecting point of the collector of the semiconductor switch 5 which can be switched off and the cathode of the diode 6 forms a second connecting terminal X2 of the subsystem 12.
In both illustrations of the embodiments of the two subsystems 11 and 12, as illustrated in FIGS. 2 and 3, insulated gate bipolar transistors (IGBTs) are used as semiconductor switches 1, 3 and 5, 7 which can be switched off. Furthermore, MOS field-effect transistors, also referred to as MOSFETs, can be used. Gate turn-off thyristors (GTO thyristors) or integrated gate commutated thyristors (IGCTs) can likewise be used as semiconductor switches 1, 3 and 5, 7 which can be turned off.
According to DE 101 03 031 A1, the respective subsystems 11 and 12 of each phase module 100 of the polyphase converter shown in FIG. 1 can be controlled in a switching state I, II or III, respectively. In the switching state I, the respective semiconductor switch 1 or 5 which can be turned off is switched on, and the respective semiconductor switch 3 or 7 which can be turned off in the subsystem 11 or 12 is switched off. This results in a terminal voltage UX21, at the connecting terminals X1 and X2, in the respective subsystem 11 or 12 being equal to zero. In the switching state II, the respective semiconductor switch 1 or 5 which can be turned off is switched off, and the respective semiconductor switch 3 or 7 which can be turned off in the subsystem 11 or 12 is switched on. In this switching state II, the terminal voltage UX21 that occurs is equal to the capacitor voltage UC across the respective energy storage capacitor 9 or 10. In the switching state III, both the respective semiconductor switches 1, 3 and 5, 7 which can be turned off are switched off, and the capacitor voltage UC across the respective energy storage capacitor 9 or 10 is constant.
FIG. 4 shows a circuit arrangement of a further embodiment of a subsystem 14, in more detail. This two-pole subsystem 14 was registered in a prior national patent application with the official file reference 2005P12105 DE, and has four semiconductor switches 21, 23, 25 and 27 which can be turned off, four diodes 22, 24, 26 and 28, two unipolar capacitors 29 and 30 and electronics 32, also referred to in the following text as the electronic assembly 32. The four semiconductor switches 21, 23, 25 and 27 which can be turned off are connected electrically in series. Each of these semiconductor switches 21, 23, 25 and 27 has a diode 22, 24, 26 and 28 electrically connected back-to-back in parallel with it. One respective unipolar capacitor 29 or 30 is electrically connected in parallel with two respective semiconductor switches 21, 23 and 25, 27 which can be turned off. The respective unipolar capacitor 29 or 30 in this subsystem 14 comprises either a capacitor or a capacitor bank composed of a plurality of such capacitors with a resultant capacitance C0. The connecting point of the two semiconductor switches 21 and 23 which can be turned off and of the two diodes 22 and 24 forms a second connecting terminal X2 of the subsystem 14. The connecting point of the two semiconductor switches 25 and 27 which can be turned off and of the two diodes 26 and 28 forms a first connecting terminal X1 of this subsystem 14. The connecting point of the emitter of the semiconductor switch 23 which can be turned off, of the collector of the semiconductor switch 25 which can be turned off, of the anode of the diode 24, of the cathode of the diode 26, of the negative connection of the unipolar capacitor 29 and of the positive connection of the unipolar capacitor 30 forms a common potential  which is electrically conductively connected to a reference-ground potential connection M of the electronics assembly 32. This electronics assembly 32 is linked for signalling purposes by means of two optical waveguides 34 and 36 to a higher-level converter control system, which is not illustrated in any more detail. The common potential  is used as a reference ground potential for the electronics assembly 32.
This subsystem 14 can be controlled in four switching states I, II, III and IV. In the switching state I, the semiconductor switches 21 and 25 which can be turned off are switched on, and the semiconductor switches 23 and 27 which can be turned off are switched off. In consequence, the terminal voltage UX21 at the connecting terminals X2 and X1 in the subsystem 14 is equal to the capacitor voltage UC across the capacitor 29. In the switching state II, the semiconductor switches 21 and 27 which can be turned off are switched on while, in contrast, the semiconductor switches 23 and 25 which can be turned off are switched off. The terminal voltage UX21 of the subsystem 14 now corresponds to the sum of the capacitor voltages UC across the unipolar capacitors 29 and 30. In the switching state III, the semiconductor switches 23 and 25 which can be turned off are switched on, and the semiconductor switches 21 and 27 which can be turned off are switched off. In this switching state, the terminal voltage UXZ1 of the subsystem 14 is equal to 0. In the switching state IV, the semiconductor switches 23 and 27 which can be turned off are switched on while, in contrast, the semiconductor switches 21 and 25 which can be turned off are switched off. In consequence, the terminal voltage UX21 of the subsystem 14 changes from the potential level “zero” to the potential level “capacitor voltage UC” which is the voltage across the unipolar capacitor 30. In the switching states I and IV, the respective energy store 29 or 30 receives or emits energy depending on the terminal current direction. In the switching state III, the capacitors 29 and 30 receive or emit energy depending on the terminal current direction. In a switching state III (“zero”), the energy in the capacitors 29 and 30 remains constant. This subsystem 14 according to the invention therefore corresponds, in terms of its functionality, to the known subsystem 11 being connected in series with the known subsystem 12.
The maximum number of respective energy stores 9 and 10 which can in fact be connected in series between a positive terminal P and the connection Lx, where x=1, 2, 3, on the AC voltage side of each phase module 100 of the polyphase converter as shown in FIG. 1 is referred to as the series operating cycle n. The maximum number of respective energy stores 9 and 10 which are actually connected in series between a positive terminal p and the connection Lx, where x=1, 2, 3, on the AC voltage side is reached when all the subsystems 11, 12 and/or all the subsystems 14 of this valve branch T1, T3 or T5 have been switched to the switching state II (U11=n·UC and U21=n·UC and U31=n·UC, respectively). It is advantageous, but not absolutely essential, to provide the same series operating cycle n between the connection Lx on the AC voltage side and a negative terminal N of each phase module 100. The subsystems 11 and 12 shown in FIGS. 2 and 3 have a respective energy storage capacitor 9 or 10, while the subsystem 14 shown in FIG. 4 contains two energy storage capacitors 29 and 30. This therefore results in a series operating cycle of n=4 for the polyphase converter shown in FIG. 1, when four subsystems 11 and 12 are electrically connected in series in each case between the positive terminal P and the connection Lx, on the AC voltage side of each phase module 100. However, if four subsystems 14 as shown in FIG. 4 are connected in series between the positive terminal P and the connection Lx on the AC voltage side of each phase module 100, then this results in a series operating cycle of n=8, since eight energy stores 29 and 30 can then be electrically connected in series. In applications in the field of power distribution, a polyphase converter such as this with distributed energy stores for each phase module 100 has at least 20 energy storage capacitors 9, 10 or 29, 30 connected electrically in series. Converters such as these are used for high-voltage direct-current transmission systems (HVDC system) or for flexible AC transmission systems, so-called FACTS.
The following explanatory notes are based on the assumption that all the energy stores in the subsystems 11, 12 or 14 of each valve branch T1, T2: T3, T4 or T5, T6, respectively, of each phase module 100 of the polyphase converter and shown in FIG. 1 each have the same capacitor voltage UC. Methods for initial production of this state and for maintaining it during operation of a converter such as this are known from DE 101 03 031 A1.
FIG. 5 shows an electrical equivalent circuit of the polyphase converter shown in FIG. 1. In this electrical equivalent circuit, the individual equivalent circuit components of each subsystem of a valve branch T1 . . . , T6 are combined to form an electrical equivalent circuit of one valve branch T1, . . . , T6.
In general, it is advantageous to design the polyphase converter such that, averaged over time, a suitable number of the systems 11, 12 and/or 14 are always being operated, such that the sum of their terminal voltages is given by: ΣUX21=n·UC (switching state II). This corresponds to precisely half of the energy stored in the series-connected subsystems 11, 12 and/or 14, and leads to a mean intermediate-circuit voltage of Ud=n·UC. This corresponds to a drive level b on the DC voltage side of 0.5, with the drive level b representing the ratio of the actual intermediate-circuit voltage Ud to the maximum possible intermediate-circuit voltage Udmax. This drive level is calculated using the following equation:
                    b        =                                            U              d                                      U                              d                ⁢                                                                  ⁢                max                                              =                                    U              d                                      2              ·              n              ·                              U                c                                                                        (        1        )            
Equivalent capacitance value of each valve branch T1, . . . , T6, averaged over time, is therefore C/m, where m=n/2. In order to prevent large uncontrolled equalizing currents flowing through the DC voltage busbars P0 and N0 between the individual phase modules 100 of the polyphase converter with distributed energy stores, the same nominal value is generally predetermined in each case between the terminals P and N of each phase module 100 for the respective voltages U11, U12, and U21, U22, and U31, U32 and this means that:U11+U12=U21+U22=U31+U32=Ud.  (2)
If the respective semiconductor switches 1, 3; 5, 7 and 21, 23, 25, 27 of all the phase modules 100 of the polyphase converter with distributed energy stores are operated in a balanced form, then, for balancing reasons, the arithmetic mean values of the valve branch currents i11, i12, i21, i22, i31 and i32 become:ī11=ī12ī21ī22=ī31=ī32=⅓·Id.  (3)
Because of the effective impedances of the phase modules 100 of the polyphase converter when the phases are being operated and loaded in a balanced form, these values are passive. The time profiles of the valve branch currents i11(t), i12(t), i21(t), i22(t), i31(t) and i32(t) therefore correspond to the following equations:i11(t)˜⅓·Id+½·iL1(t),i12(t)˜⅓·Id+½·iL1(t),i21(t)˜⅓·Id+½·iL2(t),i22(t)˜⅓·Id+½·iL2(t),i31(t)˜⅓·Id+½·iL3(t),i32(t)˜⅓·Id−½·iL3(t),  (4)
According to these equations, the valve branch currents i11(t), i12(t), i21(t), i22(t), i31(t) and i32(t) each have corresponding fundamental profiles comprising a DC component ⅓· and an AC component which corresponds to half the output current iLx(t). This combination results from the balanced operation and the identical impedances, resulting from this, in all the valve branches T1, . . . , T6 (FIG. 5).
In order to ensure the passive setting of these valve branch currents i11(t), i12(t), i21(t), i22(t), i31(t) and i32(t) the following rules should be observed with regard to the operation of the semiconductor switches 1, 3; 5, 7 and 21, 23, 25, 27 which can be turned off in a respective subsystem 11, 12 or 14:                Within one phase module 100, care should always be taken to ensure that a constant number of energy stores in the subsystems 11, 12 and/or 14 are connected in series at any given time.        
This means that, when a switching state change occurs from the switching state I to the switching state II in any given subsystem 11 or 12, or a change from the switching state I to II; IV to II; III to IV or III to I in any given subsystem 14, or from the switching state II to the switching state I in any given subsystem 11 or 12, or a change occurs from the switching state II to I; II to IV; IV to III or I to III in any given subsystem 14 in an upper or lower respective valve branch T1, T3, T5 or T2, T4, T6 of a phase module 100, a corresponding switching state change must also take place from the switching state II to the switching state I of any given subsystem 11 or 12 or a change from the switching state II to I; II to IV; IV to III or I to III of any given subsystem 14 or from the switching state I to the switching state II of any given subsystem 11 or 12 or a change from the switching state I to II; IV to II; III to IV or III to I of any given subsystem 14 in a lower or upper respective valve branch T2, T4, T6 or T1, T3, T5. With a drive level b of 0.5 on the DC voltage side, this means that the subsystems 11, 12 and/or 14 of a phase module 11 must always be switched such that n and only n energy stores in the subsystems 11, 12 and/or 14 are actually connected in series (Ud=n·UC).
If this condition is not satisfied, then this leads to undesirable and uncontrolled equalizing currents between the phase modules 100 of the polyphase converter with distributed energy stores as shown in FIG. 1. These equalizing currents are excited by a voltage/time integral ΔUph, which can be calculated using the following equation:ΔUph=k·UC·ΔT  (5)
In this case, ΔT is a difference time interval which can occur when a switching state change occurs. This difference time interval ΔT is very much less than 1 μs. The factor k is a constant indicating the difference between the number of energy stores actually connected in series in the subsystems 11, 12 and/or 14 and the series operating cycle n. If the drive level b on the DC voltage side is 0.5, then: −n≦k≦n. The equalizing currents which are excited by this voltage/time integral ΔUph can be calculated using the electrical equivalent circuit shown in FIG. 5. In order to prevent high voltage/time integrals ΔUph resulting in the excitation of high equalizing currents, the drive for the polyphase converter with distributed energy stores should be designed such that only one or only a small number of subsystems 11, 12 and/or 14 of one valve branch T1, . . . , T6 can have their switching states changed at any one time.
This measure limits the constant k to low values.
Basic profiles of the valve branch voltages Ux1 and Ux2, where x=1, 2, of an upper respective valve branch T1, T3 or T5 and a lower respective valve branch T2, T4 or T6 of a phase module 100 of a polyphase converter with distributed energy stores are each illustrated, by way of example, in a graph plotted against time t in FIGS. 6 and 7. The graph in FIG. 8 shows the profile of the sum of the two valve branch voltages Ux1 and Ux2 plotted against time t. In accordance with the control method described above, the sum of the two valve branch voltages Ux1 and Ux2 is always constant and corresponds to the intermediate-circuit voltage Ud. The switching operations illustrated in FIGS. 6 and 7 are required in order to allow the illustrated profile of the valve branch voltages Ux1 and Ux2 to be set. These valve branch voltages Ux1 and Ux2 of a phase module 100 are controlled by a higher-level control system.
According to the known control method, when the number of energy stores which are actually connected in series in the upper respective valve branch T1, T3 or T5 is changed, a corresponding number of subsystems 11, 12 and/or 14 in the lower respective valve branch T2, T4 or T6 have their switching state changed such that, in each phase module 100, a constant number n of energy stores are still connected in series in the subsystems 11, 12 and/or 14 for a drive level b of 0.5 on the DC voltage side. This results in a constant DC voltage of Ud=n·UC.
If this known method is used in all the parallel-connected phase modules 100 of the polyphase converter with distributed energy stores, this generally leads to there being no significant equalization processes in the form of equalizing currents between these phase modules 100. However, this is also dependent on the impedance relationships illustrated in FIG. 5.